This invention generally relates to dual processor data handling systems and more specifically is directed to improved means and method for switching system control from one microprocessor to another in a dual processor data processing system.
Interrupt routines are generally utilized in microcomputers and microprocessors to coordinate several kinds of asynchronous events. An interrupt initiates a subroutine call in response to some external condition (the actual interrupt) which provides a predetermined control input to the microcomputer's central processing unit (CPU) chip. This initiates execution of a specific subroutine located at a predetermined address and results in the suspension of the program being executed at the time of interrupt occurrence. The specific subroutine executed in response to external stimuli is called the interrupt service routine. These external stimuli may be the result of such events as a keyboard entry, high speed printer operation, or the presentation of data on a video display.
Typically an interrupt latch senses and holds some external event that wants to communicate with the CPU's processor. The latch "stores" the interrupt in cases where the CPU cannot immediately respond, such as where the CPU is servicing an immediately preceding interrupt. When the CPU acknowledges the interrupt, it also clears the interrupt latch.
In prior art systems when the interrupt program finishes, the last instruction in it must cause the interrupted program to resume exactly where it left off. Thus, the program typically provides some means to first save and then later restore all registers and status bits so as not to degrade the interrupted program's data. Some systems perform this function automatically, while others make the interrupt service routine responsible for maintaining continuity for the interrupted program. Most of these processors use a register stack. As heretofore described, the interrupt function is used with respect to one processor, or microprocessor in a microcomputer, for performing the aforementioned functions.
Multiprocessor systems are becoming increasingly popular because of the advantages inherent in this approach. For example, a low performance microprocessor which may be generally available and for which a large amount of machine language as well as high level language software is available may be combined with a more powerful microprocessor for performing more sophisticated, specifically tailored tasks. Or perhaps a larger memory or higher operating speeds are occasionally required, for which a more sophisticated microprocessor would be particularly adapted while for the more common, simpler operations a cheaper, more easily programmed microprocessor could be utilized. System reliability is another consideration in a multiprocessor system where one or more processors may be used as a back-up unit for the operating microprocessor. A common approach to the multiprocessor concept involves a dual processor arrangement in which only one microprocessor is active at one time with system control alternately switched between the two microprocessors.
In transferring control from a first microprocessor to a second microprocessor in a dual processor system, the prior art procedure generally involves the first microprocessor suspending its operation and relinquishing control of the data bus. The second microprocessor then goes on-line and begins executing a selected routine in its memory. This involves the interleaving of the respective codes of the first and second microprocessors. When control is returned to the first microprocessor, its operation is resumed where it had earlier terminated in response to the interrupt request. No provision is made for initiating a new routine in the first microprocessor in response to the routine carried out in the second microprocessor. This results in a substantial limitation in the operating flexibility of dual microprocessor systems.
An example of a data processing system with a plurality of processors is provided in U.S. Pat. No. 4,306,288 to Nakamura wherein a multiprocessor initialization sequence provides diagnostic routines in each processor and connects an individual processor in the system only if the results of the diagnostic routines indicate no failures therein. The diagnostic routine for a given processor is initiated in response to either a host selection signal or a subprocessor selection signal. If a failure is detected in the diagnostic routine in the host processor, the failure is registered and sent to all subprocessors resulting in the failed subprocessor being excluded from the system. Another multiprocessor system is described in an article in the October, 1981 issue of "Mini-Micro Systems" entitled "68000-Based System Features CP/M Capabilities", at page 133. The system described therein provides for the integration of the Zilog Z80 and the Motorola 68000 microprocessors under the control of a Digital Equipment Corporation PDP-11.
The present invention is intended to provide an improved means for transferring system control in a dual microprocessor system from one processor to another using currently available processor operating features. The present invention is equally applicable to a system utilizing more than two microprocessors where only one processor is operating at a given time.